Let's design and build cool (but expensive) FPGA based theremin

Here is an emailed to me webpage link showing a cost of $49, then a $29 each year renewal. This program I followed for over 10 years and is so good I would send extra to help promote his work.

https://dexpcb.com/Purchase/Full-Version

Christopher

I've finalized oscillator module (based on dewster's design).
VCC=3.3V, output: square wave 3.3V, duty cycle 50%
Voltage swing on antenna is expected to be 20..40V

Schematic:

Traced PCB: 5x6cm - going to order on dirtypcb.com

Frame for coils will be made of plastic tube with mounts:

Tube diameter is 25mm, with PCB height 6cm, 4cm will be available for winding (2cm are for mounting).

Pitch oscillator coil - D25 0.1mm winding length - 25mm: L=860uH, Q=127, oscillator frequency: ~1.44Mhz
Volume oscillator coil - D25 0.1mm winding length - 38mm: L=1.45uH, Q=132, oscillator frequency: ~1.1Mhz
Volume oscillator frequency may be lowered by soldering C10 between antenna and ground.

P.S: ordered main components:

Diligent Core Z7-10 (Zynq Z7010 - dual core 566MHz ARM with 512Mb SDRAM, and enough FPGA resources)
PMod AMP3 - stereo audio out for headphones
PMod I2S2 - stereo audio in/out for line in/out
Waveshare 4.3" 480x272 Touch LCD (B) - for GUI and controls

Going to order manufacturing of oscillator and shield PCBs after additional routing checking.

Here is an emailed to me webpage link showing a cost of $49, then a $29 each year renewal. This program I followed for over 10 years and is so good I would send extra to help promote his work. - oldtemecula

Thank you!
At least it's much more cheaper than DipTrace.

14pF load for ESD seems quite high?  The C may also be voltage / temperature dependent.  They make ESD devices that go right across RF antennas and that have very low C.

Instead of biasing the output buffer inverter to VCC/2 via R4 & R5, you can have it "self bias" to it's own internal threshold voltage (a poorly specified parameter) by using a 470k feedback resistor across the inverter I/O.  This is what I do with the prototype and it works quite well, even when the antenna voltage swing drops like a rock when your hand is on the antenna.

Have you considered using 74LVU04 instead?  It's actually designed for oscillator use, so the threshold voltage might be generally closer to VCC/2 than regular logic?

Don't forget to decouple the logic as close to the IC power pins as possible.  It makes a huge difference, particularly when using it in a somewhat analog fashion.  The 3 cap decoupling for the oscillator transistor is probably overkill, but it probably doesn't hurt either.

Have you breadboarded your circuit?  If not, I urge you to as you'll catch a lot of design weaknesses that way.  Stray C can be minimized by leaving every other row unconnected (for the oscillator) and placing the breadboard on a ~50mm or higher plastic box of some sort.

14pF load for ESD seems quite high?  The C may also be voltage / temperature dependent.  They make ESD devices that go right across RF antennas and that have very low C.

Actually DALC208 has 7pF capacity, so I have to change C in model to 3.5pF for better matching.

Of course SP721 is only 3pF, but it's harder for me to order them.

Have you considered using 74LVU04 instead?  It's actually designed for oscillator use, so the threshold voltage might be generally closer to VCC/2 than regular logic?

Unbuffered 04 is pin compatible so I can try it as well. Are 2 stages of unbuffered inverters enough for good signal edges?

What if threshold is shifted a bit? Duty cycle not equal to 50%? I believe it should not be a problem, if time of raising-to-raising and falling-to-falling edges is used.

For oscillator itseft, I've used unbuffered 04, too.
But for buffer, any logic IC may be used.
Does it make sense to try HC14 (Schmitt trigger) with the same pinout?

ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V  -- from HC14 datasheet

I've already ordered PCBs from dirtypcbs.com
If they didn't yet start manufacturing, I could change schematics.

Don't forget to decouple the logic as close to the IC power pins as possible.  It makes a huge difference, particularly when using it in a somewhat analog fashion

I believe path to decoupling C is short enough. In cases of any problems, additionall cap may be soldered directly to power pins on top of IC.

"Unbuffered 04 is pin compatible so I can try it as well. Are 2 stages of unbuffered inverters enough for good signal edges?"  - Buggins

Unbuffered slow (4000 series) CMOS tends to have low gain, so with that 2 stages might not be enough, but it all depends on what you're doing with it.

"What if threshold is shifted a bit? Duty cycle not equal to 50%? I believe it should not be a problem, if time of raising-to-raising and falling-to-falling edges is used."

I agree.  Propagation delay / rise time is more important to my stuff, not yours so much.

"For oscillator itseft, I've used unbuffered 04, too.
But for buffer, any logic IC may be used.
Does it make sense to try HC14 (Schmitt trigger) with the same pinout?"

I would avoid Schmitt trigger.  You could try it I suppose, but it has more chance of messing things up than making things better.

ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V  -- from HC14 datasheet

"I've already ordered PCBs from dirtypcbs.com
If they didn't yet start manufacturing, I could change schematics."

You can always test for this once you get them.

"I believe path to decoupling C is short enough. In cases of any problems, additionall cap may be soldered directly to power pins on top of IC."

I agree, adding a C from power to ground right at the pins is always doable.

One-two days ago there was a post about ESD protection method using 40KV cable (under this topic)?
It looks like it's deleted by some reason.

It described interesting method of ESD protection - putting 40KV cable inside "plumbing style" (etherwave-like) antennas.

If it really doesn't reduce sensitivity, isn't it an ideal solution?

Pros:
* protection is better than SP721
* no additional C which depends on T
* wire is cheaper than SP721

Contra:
* when antennas are unassembled, there will be two ugly wires visible

PS: ordered 40KV cable from aliexpress - for experiments

Is it a bad idea to put internal speakers into cabinet?
There will be 7-10cm from speaker coil to theremin coil, 10-15cm to antenna.
Speakers are 10cm size, 8cm mounting, round.
Will working speaker affect LC tank?

I have flat piezo speakers as well, but didn't yet tried if they produce good sound.
Probably, piezo will not interfere with oscillators.

"It described interesting method of ESD protection - putting 40KV cable inside "plumbing style" (etherwave-like) antennas.  If it really doesn't reduce sensitivity, isn't it an ideal solution?"  - Buggins

The arrangement forms a 40kV capacitor.  Since it's physically highly symmetrical (wire inside a tube) there is a simple formula for calculating the capacitance value (I haven't done this). The capacitor it forms can clearly withstand 40kV, but the question is: can your circuit withstand repeated human body ESD events through that capacitance? The answer is: it would take experimentation to know. Also, any series C like this will lower absolute sensitivity, but if the value is large enough the lowering will be negligible.

A while back I ran across the circuit for a lightning detector, and the front end was a high Q LC. Even distant ESD events can cause tank ringing, so simple insulation of the antenna may not be enough. Though I think it is always wise to insulate the antennas, even for tube-based Theremens, as passives (resistors, capacitors, and coils) can also be harmed by ESD. I tend to prefer the look of insulated antennas, and the antennas themselves can be formed by aluminum tape over plastic tubing, tape or very thin plates in boxes, etc.

While waiting my orders (FPGA board, LCD, audio boards, PCBs), I'm rewriting theremin sensor controller IP verilog code.

It measures oscillator frequencies (with precision equivalent to 6.4GHz counter), does scaling, linearization, distance-to-volume, distance-to-note, note-to-frequency conversions.

pitch path: oversampling_frequency_measure(4*delay_line -> 4*edge_detector -> 4*period_measure) -> scaler -> interpolation tables -> [distance, note, frequency]
volume path: oversampling_frequency_measure(4*delay_line -> 4*edge_detector -> 4*period_measure) -> scaler -> interpolation tables -> [distance, volume_multiplier]

edge_detector : ISERDESE2 based signal edge detector, 1600MHz sampling rate (DDR)

    IN -- frequency to measure - from delay line
    OUT[4:0] -- OUT[4] 0:edge detected, 1:not changed; OUT[3:0] - number of first bit with changed value1 -- updated at 100MHz

period_measure : converts edges information to period length

    IN[4:0] -- edge detector output
    OUT[11:0] -- period length (raising-to-raising or falling-to-falling) - updated on each edge (0..4096)
    READY -- 1 for one clock cycle when OUT contains new period value
    Sample output values for different input frequencies
        Input signal frequency:            4MHz  2MHz  1MHz  500KHz  390KHz
        Period length, in 1600MHz cycles:  400    800    1600  3200    4095

   
delay_line : IDELAYE2 based delay line for sub-1600MHz oversampling

oversampling_frequency_measure: x4 oversampling to increase precision by 2 bits

    IN -- frequency to measure
        input signal is passed through 4 delay lines to make 1/4, 2/4, 3/4, 4/4 of 1.6GHz delays
        each delayed signal goes to edge_detector->period_measure chain
    PERIOD[13:0] -- sum of periods measured by 4 delay lines
    PERIOD_CHANGED -- 1 for one cycle when new period value is ready
    Sample output values for different input frequencies
        Input signal frequency:            4MHz    2MHz  1.5MHz  1MHz  500KHz  390KHz
        Period length, in 1600MHz cycles:  1600    3200  4096    6400  12800  16380
        Bits of period value:              10.6    11.6  12      12.6  13.6    14

moving_average_filter: moving average filter based on 1024x18 RAMB18E1 instance with window len power of two - from 1 to 1024

    Run it once per sample (48KHz) to prepare values for next sample

    IN_VALUE[13:0] -- period value from oversampling_frequency_measure
    PUT_IN -- 1 for one clock cycle to write new IN_VALUE to BRAM
    START -- start filtering cycle
    WINDOW_LEN_BITS[3:0] -- number of bits in window length (length = 1= max ? 1.0 : (value - min) / (max - min)

    MIN_VALUE[23:0] - minimal value (from calibration - when hand is far from antenna)
    MAX_LESS_MIN[23:0] - scaling range (from calibration - difference between value when hand is far and when hand is near to antenna)
    CURRENT_VALUE[23:0] - input value to scale
    START -- set to 1 for one cycle to start scaling for provided input parameters
    SCALED[19:0] -- scaled output
    READY -- one for one cycle when SCALED value is ready

    After scaling, we have value in range 00000000000000000000 to 11111111111111111111 when hand is in calibrated range, clamping when it's outside of range.
    Actual meaningful bits are higher ones. E.g. for 1MHz oscillator with 1024 halfperiods averaging, there are 18 meaningful bits [19:2]
   
table_interpolator: interpolator based on lookup tables
       
        Block ram 4096x27bits (3xRAMB36E1) is used to store lookup tables for interpolation - populated from CPU (Zynq PS ARM Core).

        Small tables:
                  table_index  address      size    max_value        description
                  000          000xxxxxxxxx [512]  27'h7ffffff      pitch linearization table (frequency to distance)
                  001          001xxxxxxxxx [512]  27'h7ffffff      volume linearization table (frequency to distance)
        Big tables:
                  table_index  address      size    max_value        description
                  01x          01xxxxxxxxxx [1024]  27'h7ffffff      pitch distance to note 
                  10x          10xxxxxxxxxx [1024]  27'h7ffffff      pitch note to phase increment 
                  11x          11xxxxxxxxxx [1024]  27'h7ffffff      volume distance to volume control multiplier

        Tables 000 and 001 convert signal period into linear hand distance.
        Tables 01, 10, 11 are used to produce note number, F0 phase increment and volume multiplier
       
        Note number is 24-bit 6.18 floating point note number produced by table 01. Integer part (6 bits) corresponds to MIDI note number, 18 bits is fractional part.
        Pitch phase increment is value to add to 24bit phase counter per sample to obtain required pitch base frequency.

theremin_sensor_controller : AXI4 Lite slave device accessible from CPU (Zynq PS ARM core)

    AXI interface allows to read values of oversampling_frequency_measure, averaging filter, scaler, lookup interpolator stages,
    populate lookup tables, set averaging filter window length, set scaler min, max_less_min values.

    Direct output of 24 bits volume_multiplier, note_number, pitch_phase_increment values is to be passed to synthesizer DSP.
   
Probably, it makes sense to calculate differential hand position signal as well (e.g. difference between current hand position value and value several cycles ago)
to allow some synthesis parameter changes for cases when hand is mostly still, and hand is moving fast.
E.g. pitch correction coefficient might be changed to bigger values for non-moving hand, and reduced (up to 0) while hand is moving.
For volume control, differencial value of hand movement might be used to add some excitation to volume control (e.g. attack / decay / release additional control).