Well, I am much relieved! - They let me out of hospital having examined me internaly top-tail (literaly), and taken multiple biopsies - I am feeling a bit rough for it, but I dont have bowel cancer! - So, they still dont know whats wrong with me, but at least its not that!
Thanks for the candles and incense Christopher! ;-) and for all the good wishes from those here.
Ok - back to buziness:
"Just thinking out loud, but I wonder what the phase noise of the 4046 VCO is? It's almost certainly much worse than that of an LC oscillator. Not saying it's a show stopper for this application, but it could add significantly to the noise, making the SNR worse."-Dewster
The only time I noticed phase noise (VCO noise, actually) was when I was running the HC4046 without a divisor (VCO->Phase comparator input) - and I only did this when checking the interface to the oscillator (SIG-IN).. It did worry me seeing this..
However, I discovered that as soon as I put divisors between VCO Out and Comparator In (and changed VCO and filter components proportionally to the divisor) the phase noise reduced - in fact, the phase noise seems to reduce by 6db per division.. As a result of this I ran my PLLs up as high as I could (Maximum HC4046 VCO frequency is 12MHz, so I set divisor to /32, and limited max VCO frq to 11MHz, this means I could have an input frequency up to about 350kHz) and this gave a phase noise reduction of about 30db.
ADDED -> (more correctly, the noise of the divided VCO frequency being fed back to the phase comparator had greatly reduced noise - there was still a lot of noise on the actual VCO output)
As I multiplied the frequency to as high as I could and then divided the VCO down to get the required frequency, noise was not a problem.. However, in the designs I present here, I have not done that - so these designs will have more phase noise than my prototypes had... Whether this will be a problem, I cannot say.
Easiest way to rectify the above, if it is a problem, is to put a couple more dividers between the VCO output and the dividers already shown - add another /4 on both the reference and variable oscillator VFO's.
Put 1/2 74HC4520 in the VFO*16 line configured as /4 (->Clk Q1->) and the other 1/2 in REF*16 line configured as /4 (->Clk Q1->) .. The Q1 outputs driving the CLK inputs of the HC4520's already there.
Alternatively, replace the 4520's with 4040's and tap the apropriate outputs - this would also simplify division on the "register switching" design.
However, I suspect that the above 'trick' only works for analogue PLL's, as it is a direct function of the switching errors of the VCO - by operating the VCO at a higher frequency than one "needs" and then dividing this frequency down to what one actually needs, one seems to reduce the phase errors - for example, multipying the frequency by 32 (VCO = 32* Fin) and then dividing the VCO by 4, one gets the same frequency as if one had multiplied Fin by 8 - But the phase noise is reduced by 18db.
What I say above may have errors - all I know is that it works and reduces the phase noise to a level where I do not notice it and have difficulty measuring it - it may not be 6db / division, I only measured that roughly when I did /2, it became difficult to measure with greater divisors.
Fred.
(Ps - I did not show this extra multiplication on my notes or in my register-switching theremin notes, simply because I wanted to keep things simple - but adding the extra multiplication is likely to improve performance)