So sorry that so much of this thread is ending up about my Hive soft processor rather than digital Theremins. I promise to get back on the latter stick shortly.
For the last couple of weeks I've been thinking about and implementing a 16 bit literal memory channel in Hive. Since each thread has access to a dual port memory, and both ports are 32 bits wide, one could potentially read and write 64 bits each cycle, which is a fair amount of bandwidth. Each port has a single address (address port count is how ports are basically defined in FPGAs) so the 32 bit opcode port can supply a 16 bit literal or immediate along with the 16 bit opcode. Writing to this port is problematic because the address is constrained to the program counter value, so I'm not doing that. But the read gives an immediate value quite early in the cycle, so it can be used for just about anything in the pipeline. The data port access is later in the pipe so I'm only using that for data reads and writes.
I'm using this new immediate as a jump value, and freeing up space in the opcode itself means it can compare two operands rather than just the one operand to zero, and it gives a much larger jump distance (16 bits vs. 8 bits). Though of course the immediate consumes an opcode space, it executes in only one cycle along with the opcode, so there is savings of real-time. I'm not using it in conjunction with the data port so that's a bandwidth opportunity missed. I've retained the 8 bit jumps because they are efficient and I end up using them a lot.
The conditionals for the old 8 bit jumps are comparisons to zero (a==0), (a!=0), (a<0), (a!<0) which assume a is signed. These cover most conditional situations, and those they don't cover can be preceded with a subtract or XOR to give a really wide range of comparisons. In terms of two operand comparisons, equality (a==b), (a!=b) are clearly sign agnostic, but (a<b) and (a!<b) aren't. After much thought I decided to implement these only as signed, which gives a total of 8 conditionals for this new 16 bit immediate jump: (a==0), (a!=0), (a<0), (a!<0), (a==b), (a!=b), (a<b), (a!<b). Unlike one operand zero only comparison, two operand gives a natural unconditional jump by comparing (a==a) or (a!<a), and indeed I've made this an automatic substitution in the assembly language code.
I finally got the bugs out of this new FPGA SystemVerilog code, the simulator, and the assembly code this morning, and my new command line assembly code is again working with it. It's interesting and valuable to have the SV defining the hardware, the SV hardware simulation in Quartus, my C++ Hive simulation and assembler, and special verification assembly code to serve as independent checks on the correctness of the design. When they all work you've generally got it nailed. Though when the architecture changes this much (a new data channel in the PC pipeline) the churn can quite time consuming. I'm hoping this will be my final big addition for a while. The core (without Theremin logic, but with a UART and GPIO) consumes ~2600 LE (logic elements) and hits ~196MHz. With the Theremin logic, around 2/3 of the FPGA fabric I'm targeting is consumed, which is a nice comfortable point to be at. Any less and it feels like something is being wasted, any more and speed problems begin to creep in, and one starts getting nervous re. room to accommodate future changes.
I also decided to move the interrupt and thread clearing logic out of the opcode space and back into the register set space. The version register wasn't doing much, so that's now doing double duty - external interrupts can be enabled or disabled, and internal interrupts can be initiated, along with thread clears, via writes to this register.
I've only used 8 opcodes out of the free 16 spaces for these new jumps, so there is room for future addition here.
It's weird, it's taken me years to get to this point, but if I had to do it again tomorrow I could probably code up Hive in a week. Recoding the sim and assembler / disassembler would probably take months though, it's a total bear and I'm quite happy to have that behind me.
