Theremin modelling

I wanted to build a new theremin so I have selected a couple of transiter based schematics from from the Theremin World schematics page. I got the pitch reference oscilator design from Arts 145 design (http://www.theremin.us/145/145.html) and the hand drawn schematic (http://www.thereminworld.com/files/projects/handdrawn/handsch.gif). I put these into 5spice (http://www.5spice.com/) demo version and ran the transient analysis. Whilst they both started to oscilate. The analysis software showed the oscilation decaying to nothing in about 10ms. Does anyone have any simialr experience with modelling theremin circuitry?

Yes.. This is a common problem when modelling oscillator circuits - 'real' circuits often depend on transient events and 'instabilities' to get them to run 'reliably'.. Simulations do not provide, for example, real-life power-up conditions (when supply voltage turns on, it is not instant - as the supply rises 'slowly' all sorts of ambiguous states can be generated, these produce effects which are difficult / impossible to model accurately)

However - What you are having is far better than the situation which can occur, where an oscillator works in simulation but does not work on the board!

When it comes to oscillators, the best advice IMHO is to set the simulator up so that one gets the model to operate reliably, then confirm this with a simple prototype.. As in, if the simulation produces reliable oscillation, AND the board works [b] AND [/b] the maths confirms that the oscillator should work and has a good margin (particularly with regard to gain, taking worst-case component tollerances into account) then (and only then) can you be sure of the design.

Simulators vary hugely, and the simulation parameters on can set up vary hugely.. I find LT-Spice (http://www.element14.com/community/thread/1811?tstart=0)is one of the best for HF and Theremin circuits..

EW Oscillator simulation (http://www.element14.com/community/docs/DOC-16876/l/etherwave-oscillator-simulation--ltspice)

EW Front-end (http://www.element14.com/community/docs/DOC-16875/l/etherwave-front-end-simulation-antennaoscs-mixer--ltspice)


EPE 1995 Simulation (http://www.element14.com/community/docs/DOC-23483/l/a-simple-theremin-analysed-epe-1995-simulationzip)

I can see several areas of the Art Harrison circuit which could pose problems for simulation - sorry - but I dont have time to go into detail.. but my advice is to strip away everything which is not absolutely essential to the simulation.. get rid of the tuning circuit with its 'extra' diodes..

Also - I have found simulation of FETs often has problems - you need a good model, and I have not found any model of a 2n5484 which behaves like the real part.. dont know why.. but have often been forced to give up on 'real' simulation of parts using 'real' FETS or varicap diodes, and been forced to insert primitive parts and 'tweek' these to get the simulation to run... This is far from ideal, as it tells one little about how a real part will behave!

ONE OTHER MAJOR ISSUE: Some simulators configure their resolution to match the display window.. as in, if one is looking at the first (say) 100us of an analysis, smaller time-steps are automatically entered into the simulation engine than if one is looking at a 10ms window.. Loss of this resolution causes the computation to go 'flat' quite early in the simulation..

Usually, if one sets the 'window' for 100us, and the start time at 10ms, resolution is increased (time-step reduced to cater for the 100us window) - BUT - the result of this is an extremely long time before results appear (all 10ms are processed at high resolution - this must happen or the pre-conditions for the resulting 100us window cannot be computed)

Some simulators only take the end-time.. these are hopeless.

The best simulators (and the free LT-Spice is one of these) give you complete control over the simulation parameters.

Simulation is far more difficult to use than people think.. there are several levels - simple circuits are a great aid for any level of understanding.. but when one gets into the realm of non-linear circuits, oscillators etc, then one needs a lot of knowledge both of electronics and of simulation in order to get useful results.. One can spend FAR more time debugging a simulation (and learning little from doing this) than one would spend debugging a real circuit (and learning a lot from doing this).

Fred.

Way thanks!

Got it working! I have posted my LT Spice model of Art's 145 Theremins pitch oscillators up there (http://www.element14.com/community/docs/DOC-29268)as well.
Now I want to feed the audio frequencies through a parametric equalizer and feed the signal level back to the radio frequency to see if I can control the linearity.

Thank you, dcoutts -
You are the first person other than me to post anything to the
Element-14 theremin-general-resources Group (Documents) (http://www.element14.com/community/groups/theremin-general-resources?view=documents)

Have just run your simulation - yeah, looks real good! IMHO LT-Spice really makes life easier.. If I just want to simulate HF circuits, I always use it..

I use LabCentre Proteus most - but this is because I have its Ares PCB editor, so I can simulate a circuit section and then copy this section to the project and go straight to PCB design without having to re-enter the schematic.

Proteus simulations are good, but not quite as good as LT-Spice, a lot slower, and (the package is) a lot more expensive!

Having something like LT-Spice (http://www.linear.com/designtools/software/) available free, with its massive support network and frequent updates, makes (IMO) it pointless to download demo simulators.. There was a time when this was worth doing ( I ran a demo package which did not have the ability to save files, continuously for 6 weeks many years ago, as I could not afford to buy it ), but LT-Spice has changed that.

Fred.

Started making mods to my theremin model. It's so much easier than trying to tweak the real thing.
I was getting anoyted with the offset in the signal so I tried to build the second oscillator to run of a negative rail - figuring the two oscilators should cancel each others DC out. see here (http://home.iprimus.com.au/hainescoutts/bal_sup_osc.jpg)I have literally mirrored the circuit and replaced PNPs with NPNs. It didn't really work ie. I still get a (smaller) DC offset in my output. The negative supply oscillator has an DC offset of 7V for a7.5 V -ve supply which doesn't seem right. However it looks it might work if someone who did know what they were doing could unravel my mistakes. Any takers?

[i]"Any takers?" [/i]

LOL! ;-)

Man, you have gone to a lot of trouble! - this is probably the most bizarre theremin front-end I have ever seen! ;-)

Ok, not sure what you are trying to achieve, and how "DC offset" is bothering you.. but you REALLY dont need a split supply with the oscillators wired the way they are..

C18 and C4 will completely remove any DC components from the oscillators.. The buffer circuit of J3 is the correct configuration, but the selected values look wrong to me - R31 is probably not needed, and is way too low if it is needed (I would suggest nothing lower than about 220k) Likewise, R30 is way too low IMHO - You dont want to load the oscillator - and if signal levels are too high, attenuate these with a potential divider following C18, and make this dividers resistors BIG.. 100k loading for this application is way too low.

R32, on the other hand, looks too high - something in the order of 470 ohms would IMO probably be better.. FETs are funny things (particularly in simulation) - Have a look at the buffer circuits on the EPE 2008 theremin.. These work well in reality, but simulation results are poor.

I have not played with this particular circuit either in simulation or reality, and do not have the time to look in detail at it -

You say that simulating is easier than trying to tweek the real thing.. Sorry, but I have some REALLY bad news for you.. Even if you get the simulation to run perfectly, you WILL need to do as much tweeking on the real thing as you would if you had run no simulations at all!

I am not saying that simulation is a total waste of time - its not.. You learn a lot, and you have a schematic you can use to test real waveforms etc against, which does help ones understanding and sometimes helps debugging..

But what I am saying is that the notion that one can do the testing and development on the simulation, and go straight to a board which will not need tweeks or hacks because the simulator has removed this step, is wrong! Perhaps 5% of cases one does get close enough to the ideal - but 95% of the time, the simulation is just a staring point for hands-on development.

Good luck - I hope you get in the 5% ! ;-)

Fred.

Just noticed the mixer circuit..

DC offset? Are you talking about an offset from the mixer output?..

DC input to the mixer is blocked by C20 and C6.. It wont matter how one biases the oscillators or what supplies you run them off - DC potential differences will not affect the mixer input one iota..

However - There WILL be a DC offset on the collector of Q3.. Why? Because Q3 base is biased at about mid supply, and the 0.6V(ish) Vbe will raise the collector voltage above the base voltage for starters..

All simple to solve - Follow R18 with a big capacitor (22uF is usually reasonable for a line level output z).

Must admit that I dont like the mixer circuit one bit! ;-)

Fred.

Added - > And yes, there is a mistake.. The -Ve buffer is upside down.. You replaced PNP with NPN, but didnt change the N-fet for a P-Fet.

But get rid of this mirrorred scheme - it serves absolutely no purpose other than to add confusion and the requirement for a split supply!

Uh huh The P-Fet. Thanks for helping someone who may appear to have not much idea!
Partly I plan to persist with balanced supply (now I know what I have done wrong) as it works with the simluator better - I don't have to run for 5-10ms to let the transients die out as they should cancel each other out. Also my existing instrument (modified Jaycar) seems to upset amplifiers - until you earth the signal. This sounds like DC problem to me and I have growing confidence this design should avoid those problems. Also lends itself to driving balanced output in the audio stage and has a kind of symetric aesthetic that I like.

Sure, you can stay with your design..

But, in my view, there is absolutely no point in designing / optimizing a circuit for best simulator behaviour.

Reality check:

Why are you messing with this circuit? It seems, to me, that you had a circuit (the original) which you could have constructed, and would have been a working circuit by now - Instead you decided to simulate it first, using a crap simulator..

Your simulation showed a problem which was due entirely to the simulator.. This should have been a valuable lesson.. But it seems to me that you have chosen to ignore this lesson.

You are now using a good simulator - but even the best simulators give results which depend soley on the accuracy of the models used.. You are now "correcting" situations which have no relevance to the functioning of the actual circuit. (10ms start-up time makes absolutely no difference to actual operation of a theremin - doing ANYTHING to "solve" this "problem" is just a waste of effort - Complicating the design in order to "cure" this "problem" is pure folly!)

You need to ask yourself: "Why am I doing this?" - If it is because you enjoy playing with the simulations more than you enjoy building and testing actual circuits, then that is fine - you will learn a lot from it - but you will also lose a lot.. When you do get to building a real circuit based on your simulations, it will not perform as well as the simulation does, and it will have a load of needless stuff you have added just to keep the simulator happy.

You say you have problems with your Jaycar, which you believe to be DC related.. Understand this: If you have a capacitor blocking DC on the output, DC is NOT the cause of the problem!! One can have a 100mV signal sitting on 100VDC on one side of a capacitor, and you will get 100mV AC referenced to ground (or whatever potential the reference is at) on the other side.. The only time this 100V will pass to the other side is as a brief transient when the capacitor is connected.. So DC at realistic levels can cause a 'click' when connected or the circuit is powered up, but that is the only effect!

You also say: "Also lends itself to driving balanced output in the audio stage and has a kind of symetric aesthetic that I like."

Well, no - Actually.. The output audio is taken from the mixer - and this is unbalanced, regardless of how you wire the supplies to the VFO and Ref oscillators. Balanced topology is only of any use with identical signals - if the reference and VFO signals were identical, you would get silence! DC cancellation CANNOT occur and is NOT NEEDED on the REF / VFO signals by the topology you are using - ANY DC in these signals is completely blocked at the input to the FET buffers and at the input to the mixer.

" and has a kind of symetric aesthetic that I like."

You may like the look of the schematic - but the aesthetic appearance is the ONLY possible "advantage" you may get ... And for someone like me, the schematic has no appeal whatsoever as it just shouts "WTF!?" and, when analysed, proclaims that the designer was incompetent (at least).

Sorry to be so blunt - It is a great effort, and for a beginner, doing things like this is how one learns..

But the trouble is if you chose not to learn.

Please understand that I am not trying to be discouraging or critical - even if my comments above seem to be disparaging.. I think you have made a great effort and your reasoning, whilst flawed, shows that you may well become a competent original circuit designer once you have gained a bit more knowledge and understanding.

I suppose I just want to warn against over use and over dependency on simulation - And a lot of this is because I have wasted many hours due to my infatuation with the "simplicity" of design with simulation... It is difficult to get the balance right - Simulation does have its place, but it has great dangers.. Bottom line,