Let's Design and Build a (mostly) Digital Theremin!

"when I set out to make a Theremin I rashly decided to forgo all the circuitry I'd encountered on the web and start from scratch, and I often feel like a tightrope walker without a net (or a rope!).  Here I am almost a year into it and almost nothing real to show for it." - Dewster

Lol - Just 1 year ;-) ?

Yeah - If you were on a parallel universes, I would suspect we were the "same" entity - LOL ;-) .. I could have said everything you have just said - exactly - at the end of my first year wrestling with this beast.. hadnt then realised I was in her net.

- Just a few words of encouragement, LOL ;-)

I have just run some simulations looking for a phase related linearization mechanism (as you know, I have used analogue PLLs quite a lot - I tend to use phase comparator II [not XOR] when using the 4046, but build my own [which is a frequency comparator when signals are far apart, and a phase comparator as it pulls to lock] in the PSoC when I use these) and you are right - theres nothing to see.

I now have a choice - get on with my present route developing a simple Lev "clone" (for publication) and simultaneously developing a more sophisticated one (for selling) - and forget this puzzle.. Or spend my time trying to work out how, why and if I (and everyone else who has slaved over optimizing antenna equalization ) have been deluded and/or chasing a phantom.. The performance of your AFE and the results from your spreadsheet indicate that there aint much difference between compensated and uncompensated.

I think I should stay with the dark art, science be damned! LOL   ;-)

-------------------------------------------------

Oh great theremin Siren, Spirit of the Aether

I yield to your will and infinite heterodyning power.

Give me the strength and maintain my delusion, so that I can serve you without doubt or digital distractions.

Reveal to me the secrets of the dark waves which eminate from your antennas, and let me lose myself in your curves.

Signed with blood and silicon grease

Fred.

"Lol - Just 1 year ;-) ?"  - FredM

Yikes! ;-)  I really need to push ahead but when I do it often (usually) leaves me behind where I started!  Nothing like constantly discovering what won't work.

Yesterday I tried a novel approach to the dither (which is injected phase noise that helps even out the DPLL response): the MSBs of the dither vector are composed of a cyclic pattern, the LSBs composed of LFSR noise with a much longer period (previously the entire vector was this).  Then the DPLL operating point output is filtered with a moving average LPF (CIC, boxcar, etc.) that squashes the dither cycle and all of its harmonics with filter zeros.  Not a lot of difference.  In fact my desk lamp may be messing with it more due to the cyclic dither.  What I really want is a noiseless oscillator, but I can't do that with a fixed clock as the edges generally don't align.  The small amount of phase noise due to this inherent jitter is obvious when playing very near the null point (subsonic).  Maybe I should make a rudimentary DAC with an R2R ladder and use several bits to drive the tank.  I plan to lift the null with my polynomial linearization scheme, so maybe I shouldn't be worrying so much.  There's a lot of interaction between the LEDs and the pitch side, something else to confound things and fuss over. 

Worried about excess stray capacitance, today I took the AFE out of the aluminum minibox and mounted it in a plastic project case.  Replaced the CD4011B NAND gate with a 74LVU04N (NPX) hex inverter and dropped VCC to 3.3V with a LP2950 (TI) LDO.  Other than quite snappy response, a very nicely centered threshold voltage, and a somewhat higher operating frequency, there's essentially no real difference in behavior.

I could switch to an external PLL like the 4046 and just count and smooth periods, but I'd lose basic control over the oscillator, and there is still the issue of measuring with a fixed clock that will introduce the equivalent of phase noise, and here I can't easily inject dither.  However, if I did do this I could perhaps use the period, which is the inverse of the frequency, as the operating point - I'm wondering if that could possibly improve linearity (yet another simulation).  If not I could make a frequency locked loop (something you can do easily in the digital world but not the analog) and monitor its operating point. 

Phew!

You lost me! The only bits I fully understood were the stray capacitance reduction and the FLL (although I do not really understand how FLL could improve matters if you use it to maintain the antenna at resonance - Frequency locking vs phase locking? Surely, when one is in lock, these are the same? Or are you thinking of deliberately jittering the count so that phase locking does not occur, and using the average frequency obtained as the operating point?)

" In fact my desk lamp may be messing with it more due to the cyclic dither" ... "There's a lot of interaction between the LEDs and the pitch side, something else to confound things and fuss over."

This all sounds horribly familiar! - But your methods are quite different to what I was doing.. For me, it was coupling to the sensor pads which was causing the problems - these were low voltage - boosting the voltage with series inductance (tuned sensors) sorted out most of my problems.

Thing which improved SNR (before I raised the pad voltages) was decoupling any heavy switching currents (across LED or dropping resistors for example).. Can be a bit hairy though and can make matters worse, the other is putting inductors in series with these components... I was at such a desperate point (there was a Hands-off event and Gordon was going to play the instrument there - I had a few weeks to iron out these monsterous problems..... Then the event was cancelled, and I was EXTREMELY relieved! LOL ;-) I was trying anything...

Fred.

"...I do not really understand how FLL could improve matters if you use it to maintain the antenna at resonance - Frequency locking vs phase locking? Surely, when one is in lock, these are the same? Or are you thinking of deliberately jittering the count so that phase locking does not occur, and using the average frequency obtained as the operating point?"  - FredM

When you count how many system clocks there are in the external lower frequency PLL clock cycle you get the period.  I'm just wondering if the period might be more useful as an operating point number when it comes to Theremin linearity than the frequency, though I need to simulate it.  If not I have the option of locking to the frequency sans phase in order to get the reciprocal if I go the analog PLL route. 

(Several years ago I designed (originated?) a DPLL that's half FLL and half PLL - one can do frequency locking without phase locking in logic because oscillators (NCOs) can be perfectly matched; in the analog world AFAIK you pretty much have to phase lock in order to frequency lock.  And even though I understand and have an extensive analysis spreadsheet for analog XOR PLLs with integrators in the feedback filter, I couldn't come up with a sound theoretical optimization approach for it and so haven't yet used it in anything.)

(Most of what I'm doing (not that it's getting me anywhere lately) is seat-of-the-pants and not very mathy.  The main reasons to use math are to prove to one's self that something like SNR is superior in one scenario vs another (very useful and somewhat beyond me), and to dazzle everyone while obscuring how little one is actually presenting when publishing (IMO).  Excel does most of my heavy lifting, with z^-1 (unit delay) = e^(-j*2*pi*f), Zc = -j*2*pi*f*C, ZL = j*2*pi*f*L, and the complex math functions in the Analysis Toolpack.)

Now that I think about it, one thing that's probably superior about mode 1 is that it is bandpass, so it likely rolls off everything above and below the resonance point(s?).  Mode 0 is peaky (high Q) lowpass, so some of the nasty stuff below (like mains hum + harmonics) can perhaps sneak in and perturb things.  But at this point I'm kind of married to mode 0, so I'm going to do my damnedest to make it work.

" Mode 0 is peaky (high Q) lowpass, so some of the nasty stuff below (like mains hum + harmonics) can perhaps sneak in and perturb things." - Dewster

Im not sure the above is as bad as it sounds.. You say its a peaky lowpass - but I dont think this is strictly true - the series capacitor in the antenna circuit will form a high-pass filter (certainly eliminate the vast majority of low LF stuff - at least -60db at mains) so the entire mode-0 front end surely behaves more like a band-pass ?

"But at this point I'm kind of married to mode 0, so I'm going to do my damnedest to make it work."

To me, now that I am starting to get my head 'round how your circuits / system works, I can see big advantages with mode-0 for your application. Perhaps the problems are more due to the HF end (HF harmonics from switching stuff like those damn eco lights) than the low end - Perhaps something like a bit of HF filtering (say a LPF with sharp roll-off above say twice the maximum operating frequency) is worth playing with.. Perhaps even a RC LPF tuned to the max operating frequency would be enough ?

I can see that adding any kind of secondary filtering may pose problems with regard to phase detection, but with careful selection I think you could overcome such potential problems.

I may still be misunderstanding your implementation of mode-0 .. I dont actually see why this cannot be operated as a sharp BPF.

Fred.

"Perhaps the problems are more due to the HF end (HF harmonics from switching stuff like those damn eco lights) than the low end - Perhaps something like a bit of HF filtering (say a LPF with sharp roll-off above say twice the maximum operating frequency) is worth playing with.. Perhaps even a RC LPF tuned to the max operating frequency would be enough ?"  - FredM

Fred I think you're entirely correct, efforts to filter out 60Hz & harmonics haven't noticeably improved things.  Lowering the operating point from ~1MHz to ~100kHz seems to have made it more susceptible to compact fluorescent emissions.  Putting an alligator test lead on one o'scope channel and setting it near the lamp shows a ~1Vp-p @ ~22.5kHz roughly triangle wave, so odd harmonics at 22.5kHz, 67.5kHz, 112.5kHz, etc. the last of which is right on top of the current operating point!  A neat trick would be to put an adaptive filter in the DPLL loop filter, but that's beyond my current abilities and would be complex enough to pretty much require a processor.

Yesterday I looked into putting a 4046 analog PLL in the AFE.  Using the XOR phase detector would need a 3.3V rail to rail op amp in the loop filter, and I'd lose digital control over the operating point limits.  I could forgo a PLL altogether, and instead do the required 90 degree shift with a simple RC (which would be a convenient point to employ a tempco cap) but the RC would have to be adjusted for max voltage at the antenna, and if the antenna were ever changed it would need readjusting.  I'm very much opposed to these basic fiddly sorts of adjustments (beyond those easily performed by the user in software and without the aid of test equipment, e.g. linearity response - doing my best to put Thierry out of work ;-) ).

So I've decided to put that off until the DPLL proves beyond further efforts at finessing.  The NCO is currently running at 50MHz, I can easily get that to 100MHz and add accumulator logic to enable output on both clock edges for a 4x decrease in output phase jitter (did this in the past on another project).  The phase detector could benefit from increased resolution as well, something I need to think about a bit more.

Yesterday I also tried sending a delta-sigma modulated triangle wave to the AFE tank, which actually works, but splatters HF noise all over the place which makes for a noisy & sticky low end.  So back to using a square wave as stimulus.  Too bad it isn't easier getting a quality ~100kHz sine wave into and out of an FPGA.

Fred, over 10 years ago I developed a spreadsheet that I used a lot for XOR VCXO PLL design.  There's no readme in it, but it should be somewhat self-explanatory if you want to play with it:

http://www.mediafire.com/?d456yq90ac4ma9c

I used the XOR phase detector for improved noise immunity, and the lock range requirements for synchronous digital hierarchy type applications is quite narrow.  Things to watch out for in PLL design are cutoff frequency, gain and phase margins (stability), jitter peaking (over/undershoot), and ripple modulation effects (which can limit operating range).

"Too bad it isn't easier getting a quality ~100kHz sine wave into and out of an FPGA."

A simple LC oscillator, and frequncy control mechanism like varicap - and with PLL tech you should be able to get a beautiful sine from your FPGA..

When working in a noisy electrical environment, there's a lot to be said for dealing with sine waves as they are, particularly in the detection (mixing) phase of things.  Digital oriented PLLs look at edge timing, radio oriented mixers look at the whole sine wave using a continuous multiplication process, locking to a "best fit" of the entire wave.  My AFE converts (low pass filters) a square wave into a sine wave, which is OK I think.  But environmental noise can sneak into the downstream sine amplification / clipping process and move the edges around.

Inductors: I see the prototype get fairly perturbed when the clothes washer in the other room kicks on.  A ferrite rod is open to the magnetic environment much more than a closed ferrite loop.  An inductor formed on a ferrite rod has the magnetic return path through air, and so has much less temperature dependence than a ferrite loop, but much more susceptibility to external magnetic fields (and also has much less inductance).  So I'm wondering what portion of the interference I'm seeing with the Bournes 6310 inductors is magnetic field rather than electric field, and if I'd be better off with a closed loop ferrite (with more aggressive tempco methods) to eliminate magnetic interference?

I'm working on improving the DPLL I/O timing so that less dithering and averaging is required.  There is a phase offset mechanism in the Xilinx Spartan 3 DCM, but they made it less general in later generations so I'm kind of afraid of using it (too bad because it gives +/- 1/255 of a system clock cycle resolution).  What I'm doing now (haven't quite finished the coding though very close and have done some speed tests) is to run the DPLL at 150MHz rather than 50MHz, and have the NCO kick out two bits of phase info rather than one (the square clock) which will be routed to a DDR pin, giving 3.3ns resolution (vs. 20 ns).  The phase comparator will have a similar DDR input and two bit logic to increase the resolution there as well. 

It's really OK as is, but I keep watching videos where people play the Theremin from what looks like half a meter away at medium and high pitches and getting envious (the SNR on mine poops out around 2 feet or so).

"My AFE converts (low pass filters) a square wave into a sine wave, which is OK I think.  But noise can sneak into the downstream sine amplification / clipping process and move the edges around."- Dewster

You may well be right.. I put the failure of my early attempts with digital (which used square waves and PSoCs) down to signal levels - which seemed to be confirmed when I boosted the levels using inductors.. But these inductors also meant I was dealing with sine waves on the antennas - I needed to convert these back to logic levels, for which I used RC attenuation and zero-crossing detection. It may well be that my assumptions regarding the primary failure mechanism was not a complete explanation or completely correct - (or even at all correct, LOL ;-)

 "if I'd be better off with a closed loop ferrite (with more aggressive tempco methods) to eliminate magnetic interference?"

Oh, I dont think there is any doubt that a closed inductor or torroid greatly increases immunity. One big problem with open (rod) ferrites is the directional nature of the fields and sensitivities - I noticed this when using those horrible cheap axials - Even when I got the 3d "theremin" working, it could misbehave if I changed its orientation with respect to some other appliance.. I even sometimes wonder if it only worked when oriented E-W LOL ;-)  .... And yes, I have found analogue is not subject (or certainly not noticably / measurably so) to these kind of problems.

I was not so tenacious back in those days - I tried some things to reduce the problems, but it was rapidly dawning on me that the instrument was unplayable even when everything was working - and the idea of producing an even more difficult (and even stupider) instrument than the theremin caused me to abandon it.. But one thing I did try which did seem to help, was to line the tubes in which the inductors were housed (I had plastic tubes - actually medical sample containers - covered in foil which was actively driven with a shielding signal..) with non-magnetic fridge magnet material (a flexible rubber / ferrite stuff one can buy cheaply - intended for fridge magnets, but easily demagnetised).

I think the above sort of "fiddle factor" is just ok if one is building a one-off, are in a tight spot and need to fix a problem, or you are just testing concepts -  But its absolutely useless if one is designing for manufacture.. unless one has the funds to get special parts made based on what one learns.. And there just isnt any sense in going too far on investing too much - One could easily spend as much on just sorting out the inductors / shielding / tempco to get these 'perfect'  as it costs Moog to produce their whole theremin - and most people are happy with that instrument! 

"So I'm wondering what portion of the interference I'm seeing with the Bournes 6310 inductors is magnetic field rather than electric field, and if I'd be better off with a closed loop ferrite (with more aggressive tempco methods) to eliminate magnetic interference?"

You should be able to get some idea about this from what happens as you change the 6310's orientation.. In my expierience, one gets huge changes if one moves (rotates) the inductor on the horizontal axis, or flips it from horizontal to vertical.

Fred.

"You should be able to get some idea about this from what happens as you change the 6310's orientation.. In my expierience, one gets huge changes if one moves (rotates) the inductor on the horizontal axis, or flips it from horizontal to vertical."  - FredM

Maybe do a "humbucking" arrangement where the two inductors (tank and EQ) face opposite (180 degree) directions?  Any externally applied field would then tend to cancel.

I'm still thinking closed ferrites (or better yet pot cores) are perhaps the final solution.  Too bad those CMCs you were looking at didn't pan out.