Let's Design and Build a (mostly) Digital Theremin!

Hi Dewster,

Cannot get my head 'round your tuner layouts at all ;-) but I think that with layouts like this its often only the inventor who "gets it" at first - as for keyboards, the first mono synth I built as a kid, I had just discovered binary - so had a one hand binary coded keyboard into an R2R - I thought I was a genius.. until I tried to play it! - Sequencing binary with my fingers was not as natural as I expected it to be! ;-)

I REALLY like your oscillator design - Your use of an inverter (well, a couple) to implement the equivalent circuit of a differential amp / BPF is really clever - you may not like analogue, but you are damn good at it! - in fact, your implementation is far simpler than what I would have come up with - I am a bit stuck on avoiding things like inverters for analogue stuff, and end up using the 'proper' parts - but for applications like this what you have done is much nore elegant, simpler, cheaper, and as, if not more efficient - and equally reliable.

I may just try using this oscillator in my PLL scheme - Put the tuning capacitance between the 1k+9k node and the inductor (probably an opto controlled capacitance in parallel with another C) - getting rid of the frequency dependence is a big + !

Fred.

"I REALLY like your oscillator design"  - FredM

Thanks!  It's not entirely ideal, but it seems to work OK on the breadboard. I may play with it a bit more - I wonder if the gain were reduced to just enough to keep it oscillating, with the last inversion stage given a gain of 1 to be linear, if that would help the phase noise.

If the phase noise isn't an issue (remains to be seen, I can't characterize it) then perhaps it could form the basis of a resurrected TW Theremin?  There would be no real tuning other than setting the heterodyning frequency for null.  An untrained monkey could do that.

"perhaps it could form the basis of a resurrected TW Theremin? " - Dewster

I think it has potential -

The only problem IMO is that there is no antenna equalisation (despite having a big antenna-side inductor) - Fr will be directly determined by C'ant and this inductor (which is in fact a series tank inductor, not an antenna linearizing resonator)

So one needs (if you are bothered about linearity / playability) to implement this further down-line. 

Of course, the whole issue of linearity has become something of a mine-field - Do we need it ? Did Lev or Bob achieve it with their antenna resonators, or did they just fit those to waste money and make the theremins look fancy ? And among other things, some theremins are playable without linearizing coils...

An issue I aint getting involved with anymore ;-) .. I personally dont think TW is structured or moderated in a way that any "TW Technical Project" has any chance -

Fred.

"There would be no real tuning other than setting the heterodyning frequency for null.  An untrained monkey could do that."

Hmmm .. not so sure about that! ;-) .. Having seen some famous rock musos tuning /  playing a theremin such that pitch increased as distance increased (ie playing in the wrong-side-of-null field) I think one needs a wrong-side indicator at least, and ideally wrong-side muting ;-)

After all - theremins usually operate in this way, tuning the reference frequency.. If one has an oscillator which is tollerant to a wider variation in antenna capacitance, and wishes to exploit this, one needs a similarly wide frequency adjustment on the reference oscillator, making this adjustment courser and possibly more likely to drift.

Sorry to bring it back to my "upside down" topology - but that is possibly one of its big advantages - If one has a PLL error voltage which gives say a 4V change over normal playing, but can track deviations to produce say a 10V change, then one can have gross background capacitance variation - "nulling" is simply a matter of adding / subtracting a bias voltage before the modified error voltage is fed to the 'slave' oscillator.

And your series oscillator looks ideal for this, and even phase noise (if its there) probably wont be a problem after the error voltage filter and other filtering in the CV modifier are in its path.. all I need to finalise is a tuning scheme that the PLL can use to lock this oscillator over a wide variation of antenna capacitance.

Its back to the (IMO) fundamental flaw in the conventional theremin topology - producing the audio directly from the antenna front-end oscillator... Get rid of this constraint, move the (analogue) processing and audio generation away from the antenna, and you can optomise both the antenna side and the audio production independently.

With every digital theremin topology, this is how things happen - But its only done this way with a few analogue theremins (2?), and mostly (if not all of) those employ other methods to produce the sound and dont use heterodyning.

"Of course, the whole issue of linearity has become something of a mine-field - Do we need it ? Did Lev or Bob achieve it with their antenna resonators, or did they just fit those to waste money and make the theremins look fancy ? And among other things, some theremins are playable without linearizing coils..." - FredM

I believe there is something to linearization, but I don't think it's worth doing in the pitch oscillator itself due to the factory and ownership tuning problems it brings with IMO too little benefit.  And, except for sound effects type playing, I don't see Theremin players going near the pitch antenna much during pieces, so linearization may be largely moot.  I think linearization of the near field is worth pursuing in higher end instruments, but by other means as you describe (decoupling of functionality).

"An issue I aint getting involved with anymore ;-)"

Sorry to pick that scab!  I think it's still worth doing, but I don't have gobs of spare time to devote to it (yet, paradoxically, I have plenty of time to gab on TW!). 

It would be neat to use PWM somehow to control the volume, and I think I'd make the pitch knob a 10 turn pot or similar.  I believe the XOR of two square waves would give a triangle? 

" I believe the XOR of two square waves would give a triangle? " - Dewster

Yes - but with a D-Latch and a bit of logic, you can easily produce ramp and other waveforms..

http://www.element14.com/community/thread/18199/l/mixed-signal-waveshaping-and-heterodyning

"Yes - but with a D-Latch and a bit of logic, you can easily produce ramp and other waveforms.."  - FredM

Thanks for that Fred!  Schematics, waveforms, and everything!

I wish someone made a $10 CPLD (or equivalent) board, you could pull most of this stuff into it along with reference NCOs, modulators, displays, etc.  But once you start down that road it's hard to reign in expectations.  Pure analog, or mixed with CMOS, can get fairly complex, but with digital the sky's the limit.  When the heck is it a "real thing" and not something that could obviously be improved given a bit more logic, ingenuity, and effort?  This, I think more than anything else, has stymied me with Theremin design.  I wrestle with it every day, searching for a form that feels somehow complete.

"I wish someone made a $10 CPLD (or equivalent) board, you could pull most of this stuff into it along with reference NCOs, modulators, displays, etc. " - Dewster

I really wish one could still get 22V10 PALs in DIL - They were wonderfull for mopping up logic - Even the MACH4 CPLD's are too expensive when one adds a good quality PLCC socket really - I can get a PSoC 5 for less, and it does ALMOST everything one needs --- But its that damn "ALMOST" which is the killer -

When it comes to combined logic "mopping" and processor in a chip, you have now converted me to FPGA's - Oh, I havent messed with the processor stuff yet, but can see that I could - And I can create programmable dividers, PWM's, phase comparators, and any logic based functions far more easily with the FPGA than any other part I have played with to date - And the clocking speed knocks the sh*t out of anything any PSoC can do...The whole digital heterodyning / waveshaping stuff in that article can be mopped up in an FPGA (or PSoC 3,4 or 5) - Sadly though, the PSoC-1 doesnt have any D-Latches, and the ones I have created using the sparce logic available havent worked well - which is a real pain, because these parts are cheap and DIL - Having to tack a 74HC74 onto it just to get the latch function is a real pain. 

So I can see your reluctance to go analogue any more than you absolutely must - For me, I dont care what I use, if the results are ok - The idea of having everything done in one main part is tempting on every level - And if you can do that, I think you are onto a winner (or as much as one can be when talking about theremins ;-) .. But I must face the fact - I am not skilled enough in that particular art - If I had 5 years to play with the FPGA .... But I dont.. My use of FPGA's will be shameful! - I may use them to do dividers and PD's and waveshapers, and to implement the UI - But I will still need analogue oscillators and filters etc, simply because there are some things well beyond my ability.

Fred.

"When it comes to combined logic "mopping" and processor in a chip, you have now converted me to FPGA's - Oh, I havent messed with the processor stuff yet, but can see that I could..."  - FredM

I think I'm kind of a freak when it comes to digital stuff.  It all started out rather innocuously with CPLD mop-up, but a couple of years later I spent months coming to grips with DPLLs in order to wipe a ~$20 part off of our broadband master controller and system timing board.  I also designed a TSI (time slot interchange) FPGA component to wipe a ~$30 part off of our voice controller board.  Processor design alone has taken a couple years out of my life, but I'm really only up to it lately, ~15 years now into full-time digital.

"But I will still need analogue oscillators and filters etc, simply because there are some things well beyond my ability."

There is another level or two of abstraction that digital introduces to audio and other analog processes.  I handle it with spreadsheets and the now dead Quartus simulator.  I'm not sure how others do it, but from what I've seen most people just dabble, even ones that are well paid.  There isn't a lot of real caring out there in the professional world.  I've worked with some great designers, but also with more hacks than I imagined existed in EE.

A friend of mine used to play every flight sim he could get his hands on.  I stayed away from the modern ones (>WWI) because there was always too much to learn about the interface, let alone flying jets.  But one day he gave me a quick tour of F15 Strike Eagle III, and I was up and doing missions in no time.  (The clouds and sky, particularly at sunrise/set, were beautiful in that game.)  Anyway, I'm sure some minor coaching could get anyone up to speed on the Quartus simulator interface fairly quickly.  I can't say any book or class I've had on VHDL or verilog really helped me in any way though.  I learned a lot more looking at real code generated by others, and from the multitude of Altera and Xilinx design guides.

Having the tankless analog oscillator on my bench just sitting there waiting to oscillate at a moment's notice encouraged me to test out a sense winding on the Bourns 50mH choke today.  100 turns of 34 AWG on the drive end with a 4.7k parallel load gives ~6V p-p quadrature sine.  The windings are right up against the stock end winding, so I think there is a certain amount of capacitive coupling, something a plastic bobbin would probably help ameliorate.  Loads lower than 4.7k appear to start excessively loading things.  50 turns with the same 4.7k load gives ~2.5V p-p which is in the ballpark of what I'm looking for.  With so many stock turns on the Bourns inductor, I'm kind of amazed that it only takes 50 or so turns to give a reasonable amplitude sense signal.

" I'm kind of amazed that it only takes 50 or so turns to give a reasonable amplitude sense signal." - Dewster

I have been surprised by exactly the same thing !  I assumed it was some deep misunderstanding I must still have about inductors / coupling etc.. But to be honest, have been a bit embarrased to ask - so I trawl through what I can find in the hope that I will stumble on the answer (I usually do ;-) and say OMG! Its obvious! How could I have been so stupid!

You see - I actually have a problem understanding voltages / currents coupled in transformers - its an area I dont have clear visualization in.. Particularly when the primary is part of a series LC - What is the primary voltage ?

I am inclined to think that the primary voltage is, well, the voltage across the primary ;-) ... With a series LC, this can be quite large (easily 200V P-P) so say your primary is 250V P-P, 50 turns = 2.5V P-P ratio us 100:1 so one would expect primary to have 5000 turns ..

Looks ok ish ... If it worked like that - But I have rarely found that it works like that in practice. (it all seems to depend on wire thickness, where the windings are in relation to the core, and stuff like that - number of turns is the main factor, but there seem to be many other factors which completely screw up any attempt at simple calculation of required turns)

And im not sure the above hypothesis is correct. One thing you could do is measure the inductance of your 50 turns, from this calculate the cores AL (roughly) and from this deduce the number of turns on the primary (roughly) - This may give an insight to whats going on.

Fred.