" I suspect it is possible to have a fundamental frequency emerge from heterodyning that has zero crossings which don't directly align with the edges of either square wave input?" - Dewster
Im not sure about this - but more to the point not sure it would matter.. once the signals are mixed in the XOR, isnt the only thing of importance (in terms of cross-over) the M:S ? And if the zero crossing (50:50 MS) didnt align with the input clock/s, would this matter? - As I see it, one could set the "crossing" threshold wherever on wanted (compare the PW against some constant) - comparing M to S just seemed like a way to get higher resolution.
Please dont worry "not an attack" - I need to bounce ideas like this as a form of sanity checking! ;-) - And yes, determining the X-Over with any precision is going to be difficult - Higher frequency clocks, lower frequency oscillators (or pre-division of these oscillators) and large offset difference frequency will be required if I want to get much improvement on a simple D-Latch.. For most (perhaps all) applications, this idea probably isnt worth the design effort let alone implementation... I never realized this when I posted the idea, but I do now - largely because I set out to prove that I was right by doing comprehensive simulations, and these showed that I wasnt as "right" as I thought I had been! ;-)
But as with all ideas, unless shared, one cannot get feedback - and ideas (and the feedback) can get others thinking about things differently and perhaps finding solutions or generate new ideas.. And if (and sadly, this is where it falls down) others then expose their ideas (rather than skulk off and secretly exploit others freely given work) then things advance.
Fred.
Oh, BTW - I do agree that with analogue integration of an XOR PWM, one does need as high order filter as you can manage - the better the filter, the more accurate the detection seems to be - For the job I am looking at using this design on, I have been using a 4 stage CMOS buffered LPF.. This design is absurdly cost critical and space constrained, which is one reason I am looking at eliminating the analogue integrator and comparator, and hoping to use a small low cost PSoC 4 ($1) - But I will be also be looking at using the PSoC filters and comparator UM's - this will probably do the job better - and I can have XOR, filter and comparator in the chip so still (hopefully) achieve what I need.. perhaps with one external RC.
-> LOL ;-) I cant just let this go.. Now gone back to ,my D-Latch scheme - I think that using the clocking ideas above I can actually count the error component using the period clock and capture this, which would allow this valur to be simply added or subtracted from the period count.. stay tuned - another probably silly idea is likely to come soon ;-)