Mo' MIDI, Mo' MIDI, Mo' MIDI
Several days ago I made Mute 0=>1 send MIDI note-off and all sound off. The "all sound off" command is rather mis-named, as any note that is playing will not stop (!) hence need to send a separate freaking note-off (actually note-on with velocity = 0, which should be a damping command if you ask me, but MIDI's gotta MIDI, everybody does it, etc.). I've read that sequencers deal with this (yet another) glaring hole in the standard by sending out a flurry of note-offs just to cover this hugely uncovered base. I also made MIDI chan=0 (an oddly invalid value which causes all sorts of mayhem at the lowest level dealing with it - "do you mean the real channel 1 or the user channel 1 (0)?" - and how do you represent it in SW, as -1? If so you have to make sure you don't actually use it as a channel!) now inhibit all MIDI TX activity, including these mute commands, which seems like the right thing to do. Also shuffled the knobs a bit and renamed the tloc knob to vloc, to make it clearer that it corresponds to the velo sense point (this is also the note on/off trigger point).
If one were guaranteed a wide pitchbend on the other end, one thing I was thinking would be to permanently center it on like A440. This would guarantee no retriggering going on outside of what can otherwise be a rather random range. Maybe move the fixed center point around with the oct knob? Just a thought.
For the past few days I've been really giving all SPI EEPROM code a thorough comb-over. In the process I've managed to erase my entire user preset space (not the read-only space, which figures) and of course I'm an idiot for not taking like one minute to back everything up. But not too much of an idiot because I tend to snag presets that I like with the librarian. Was able to get my system preset back by looking at editor screen grabs posted here to TW (OK, I'm an idiot) then found the ptoe_sys, ktoe, and etok commands would do it too in a roundabout but faster way. Broke my P3 for over a day which always freaks me out for some reason, computing is a house of cards all the way down, and I guess I find staring that fact in the face for any length of time fairly unbearable. Part of it was not quitting for the day and archiving it when it was working, but instead going for the gold and ending up holding a turd. Part of it was not holding my jaw right when rebuilding the FPGA, confounding what revision I was even working with. Much of it was changing too much at once and getting lost in the complex symptoms. It's always something stupid.
Anyway, P3 is back in business with much more consistent chip select management (the first line of defense is keeping the chip de-selected whenever possible). These changes have rippled over to the librarian code too. It turns out I actually located the preset and SW EEPROM regions correctly for optimal write protection, and I've got a subroutine to expose / protect just the preset region while keeping the SW region protected (but have that commented out for now, one thing at a time).
The default FPGA SW load could/should have something indicating to the user that an error has occurred in loading the EEPROM version of the SW. Processor insanity could possibly corrupt the SW region, but it could be uploaded again with the librarian. I could put a jumper on the EEPROM write protect pin, but that would leave the presets more exposed with no write protection possible, and would make updating the SW more fiddly for the user. The boot code is actually a subroutine, and my plan is to have that return a flag or other value indicating good/bad boot, with non-boot code writing this status to the LCD somewhere / somehow. Boot code is rather set in cement in the FPGA, and unfortunately (or fortunately!) can't be updated with the rest of the software, so it needs to be kept as small, simple, yet flexible as possible.