Thanks for your offer of help, Dewster..
Have now moved from angry frustration to actually finding it quite funny! - When I talk about using PWM blocks here, its at simplest most trivial level - all I need as two dividers that can either be programmed to divide be 2,4,or 8,and / or a pair of counters tapped at 1 (input) 2, 4 and 8 going into a MUX..
It was bitter enough having to dedicate two complex 16 bit TCPWM blocks for something so trivial (at first I created a specific UDM component for the job, but soon found that I had run out of UDM resources, so moved this function to TCPWM blocks, and everything fitted and ran well - when using clock-chain clocks )
I am now going back over the UDM components to see if I can implement some in LUT state machines.. The fitter report is not detailed enough (doesn't give the equations for the fitted logic, which is a major bummer - perhaps it does when it actually manages the fit) but I think the bottleneck is with the registers (DFF and the like)
I have seen an "escape" route - Not a route I really wanted to go, but if I must.... I had planned on a basic build with just 1 PSoC4, and limited user control implemented with potentiometers- this was going to have a serial port for communication with a second board having a comprehensive digital user interface and more audio processing stuff.. The idea was that the first board had place for digital potentiometers and was wired ready to drive these, but on the simple theremin the digital pots would instead go to manual user pots... these being replaced by digital pot IC's if the second board was added (the idea was to simply have the manual pots wired to headers which plugged into the IC sockets intended for the DPots)
I really wanted to keep the first board a simple stand-alone theremin with register switching.. The second PSoC will need almost no UDB resources -so I could palm off the register switching to this one, and make the first board a non-register-switching stand-alone theremin.. This route probably makes a lot of sense even from a selling perspective - But its still frustrating.. Adding register switching for the cost of a selector switch, and using resources inside the chip which cost no extra - for that to be inhibited by something stupid really annoys the hell out of me!
Fred.
Ok - Got some feedback.. This issue only applies to the PSoC4, not to the 3+5.. PSoC4 is quite restricted and its a big mistake to think its similar to the 3 or 5 - its a low cost cobbled down part.
>> Update:
Ok - I am an ignoramus! ... I have just discovered a whole suite of deep-level editing tools for the UDB.. I have only been playing with the tip of the iceberg (the logic gates etc available in the main component catalog) and linking these to make 'components' ... But hidden away, each UDB has a dedicated state machine, data-path block, a counter, status and control registers.... And all of these can be accessed with a dedicated UDB editor, complete with Verilog code generator.. The only problem is, it will take me longer to read the damn manual than it took to put the whole design together..
>> Update:
A few small changes to the 'components' (after understanding the PLD structure better) and I was easily able to fit the additional logic to implement register switching, and have spare capacity (fitter now tells me I have used 56% - but I dont trust the fitter one bit ;-)
The fitter was telling me, before I made some minor adjustments to the components, that I needed another 4 UDB's to fit the design! (there are a total of 4 UDB's in the device) .. It should have been able to re-route the resources automatically IMO..
You are right, Dewster - Its the tools that are probably the biggest problem, not the silicon.